A novel digital control for DC/DC converters to improve steady-state performances

This paper describes an innovative digital PWM control implementation for low voltage, high current DC-DC converters. The proposed technique, based on the use of a low resolution DAC, improves steady-state performances, minimizing limit cycle effects. The novel technique is tested on a FPGA-based single phase buck converter operating at 250 kHz. A detailed description of the proposed architecture is given and test results, simulation and experimental ones, are shown