A Fourth-Order 18-b Delta-Sigma A/D Converter

Oversampled analog-to-digital converters (ADCs) are attractive for VLSI implementation because they are especially tolerant of circuit nonidealities and component mismatch. For higher-order sigma-delta (Δ) modulators, the multistage noise shaping technique (MASH) Σ-Δ modulator architectures are often to be adopted to avoid instability problems. A CMOS 18-b fourth-order Sigma-delta ADC is described in the paper. The integrated circuit contains a fourth-order delta-sigma modulator and decimation filters. With an oversampling ratio of 128 and a clock rate of 6.4 MHz, simulations show that the ADC achieves a dynamic range of 109dB and a peak SNR of 108.2dB over a 22 kHz bandwidth.