Hot-Carrier Reliability of NLDEMOS in 0.13μm SOI CMOS Technology

This paper presents reliability investigations in NLDEMOS transistor in 0.13μm SOI CMOS technology. Reliability tests under hot carrier injections (HCI) for different gate-lengths show two different degradation mechanisms. The modification of current path with short overlap (O
_lap
) due to oblique equi-potential lines and the increase in the vertical electrical field under the gate edge at low V
_g
lead to distinguish N
_it
interface trap generation from the source side injection