High frequency LNA design in Standard CMOS process

The high frequency LNA design in standard CMOS process is discussed. The traditional cascode architecture is compared to the common source configuration. It is shown that at high frequency of operation the use of a common source first stage leads to a lower noise figure. Design of two K-band LNAs with lumped elements matching cells or distributed matching cells is presented in a 0.13 μm standard CMOS process. Simulations show a noise factor of 3.1 dB with a power gain of 18.6 dB for 30 mW power consumption