A 2.5-Gb/s Receiver PDIC With Low-Noise Integrated Charge Pump

A single-chip optical receiver with integrated voltage-up-converter for speed enhancement of the photodiode in a 0.6-mum silicon BiCMOS technology with f
_t
=25 GHz is presented. It incorporates a vertical p-i-n photodetector with responsivities of 0.36 and 0.26 A/W at 660 and 850 nm, respectively. Using an on-chip low-noise charge pump (CP; V
_OUT
=12 V) at a bit rate of 2.5 Gb/s and a bit error rate of 10
^-9
, sensitivities of -23.5 and -21.2 dBm are obtained for 660 and 850 nm, respectively. The basics of the current-driven regulated low-noise CP are presented