Model-based verification of batch process control software

The paper describes an approach to verify control software for batch processes. We look at logic controller programs specified as sequential function charts (SFCs). The basis of the verification is a Boolean condition/event (BC/E) model of the uncontrolled behavior of the batch plant. The control program to verify is translated into a BC/E system representation and then connected to the plant model. The verification process consists of a comparison of the set of reachable states of the resulting system and a set of forbidden states. The approach is applied to an existing lab plant.<
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