Fully-parallel multi-megabit integrated CAM/RAM design

Previous implementations of large-capacity Content Addressable Memories (CAMs) have employed advanced fabrication techniques or serialized operation. This paper describes a more generally applicable fully-parallel solution based on circuit and architectural innovation. A "pre-classified" CAM is integrated into the same array as its target RAM, and both use the same core cells. Architecture and operation are described, as are two critical-path circuits: the match-line pull-down and the multiple match resolver. An 8 kb test chip is described, and simulation results for a 1 Mb configuration are presented.<
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