A fault-tolerant multiprocessor cache memory

In multiprocessor systems, cache memories serve two purposes, namely the reduction of the average access time to the shared memory and the minimization of interconnection network requirements for each processor. However, in a cache, interference between operations from the processor and operations for data coherence degrades the cache performance. We propose a cache with only one single dual-port directory which can be operated for both processor accesses and coherence operations simultaneously. The cache can reach high performance at low cost. This cache also has a coherence-protocol-independent structure. In order to improve the reliability of the cache, we design a tag self-purge mechanism, a comparator checker, and a totally self-checking checker for an (n-1)/n code in CMOS technology at low cost in the cache management unit. Moreover, the total hardware overhead is low, compared to the traditional single directory cache management unit.<
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