A 500 ps 32 /spl times/ 8 register file implemented in GaAs/AlGaAs HBTs [F-RISC/G processor]

A high speed register file has been designed that is well-suited for achieving the speed potential of a fast but yield-limited technology such as GaAs/AlGaAs HBT. Descriptions of address driver, write, and threshold voltage generator circuits developed are presented. The test strategy utilizes two linear feedback shift registers (LFSRs) to provide address and data patterns to the register file. A match circuit verifies valid memory function and indicates read access time. The test results indicate a read access time of 500 ps.<
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