An architecture-driven approach for the fitting problem in an application-specific EPLD

An architecture-driven fitting algorithm for an application-specific erasable programmable logic device (EPLD) is described. The specific architecture-dependent constraints imposed on the connectivity of the chip are used to develop a hierarchical partitioning structure of the algorithm. This approach limits very effectively the solution search-space in the early stage of the search process. The program which implements the proposed algorithm has been tested, and the experimental results are very promising. The approach which is based on partitioning can be also applied to other field programmable gate array (FPGA) architectures.<
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