A hierarchical multiprocessor architecture for video coding applications

A hierarchical multiprocessor architecture for real-time video coding applications is presented. Due to the properties of actual video coding standards, two strategies can be utilized for parallelization, data distribution and task distribution. To exploit the advantages of both approaches, a combination of the named strategies is used in the proposed hierarchical multiprocessor architecture. For optimization of the architecture, an efficiency measure is introduced which considers processing time, silicon area, and the yield of the semiconductor process. Results are given for an implementation example.<
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