A VLSI architecture for vector quantization with optimal search

A VLSI architecture for vector quantization (VQ) problems such as real-time image coding is proposed. The encoding process applied is independent of the vector dimensions and does not perform any arithmetic operations. Each processing elements in the VLSI is a magnitude comparator. The decision tree is generated by an offline process. Together with pipeline architecture, high-speed encoding is now realizable in a single chip.<
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