An area-efficient maximum/minimum detection circuit for digital and video signal processing

A circuit for parallel bit-level maximum/minimum selection is presented. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from most significant bit (MSB) to least significant bit (LSB) and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns such as those required in digital and video signal processing.<>