Spur-reduced digital sinusoid synthesis

This paper presents and analyzes a technique for reducing the spurious signal content in digital sinusoid synthesis. Spur reduction is accomplished through dithering amplitude and phase values prior to wordlength reduction. The analytical approach developed for analog quantization is used to produce new bounds on spur performance in these dithered systems. Amplitude dithering allows output wordlength reduction without introducing additional spurs. Effects of periodic dither similar to that produced by a pseudo-noise (PN) generator are analyzed. This phase dithering method provides a spur reduction of 6(M+1) dB per phase bit when the dither consists of M uniform variates. While the spur reduction is at the expense of an increase in system noise, the noise can be made white, making the noise power spectral density small. This technique permits the use of a smaller number of phase bits addressing sinusoid look-up tables, resulting in an exponential decrease in system complexity. Amplitude dithering allows the use of less complicated multipliers and narrower data paths in purely digital applications, as well as the use of coarse-resolution, highly-linear digital-to-analog converters (DAC's) to obtain spur performance limited by the DAC linearity rather than its resolution.<
>