A low ROM distributed arithmetic implementation of the forward/inverse DCT/DST using rotations

In this paper, we first propose an algorithm for computing the DCT and IDCT using rotations. Then, based on the proposed algorithm, we present a unified VLSI architecture for the real-time implementation of the forward and inverse 8/spl times/8 DCT and DST. The rotation circuit which is the main processing unit of this architecture, is realized with distributed arithmetic using the binary offset coding strategy. Exploitation of the rotation properties results in a reduction of the total ROM requirements of the unified architecture, to less than 10% of those of the typical distributed arithmetic DCT/IDCT implementations, thus yielding considerable area savings. Moreover, the proposed architecture can achieve the processing power of 100 Mpixels/sec, if implemented in 0.8 /spl mu/ CMOS technology, which is sufficient for the real-time processing of HDTV signals.<
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