A 3.0 V 40 Mb/s hard disk drive read channel IC

This paper presents a high performance low power BiCMOS mixed signal ASIC that integrates all the electronics required by a hard disk drive (HDD) read channel. The IC includes the automatic gain control (AGC) circuit, a programmable continuous-time filter, two pulse qualifiers, the servo demodulator, the time base generator, the data synchronizer, and the encoder/decoder. Constant density recording with data rates between 14 and 40 Mb/s in 1,7 Run Length Limited (RLL) format and embedded 4-burst servo are supported. All the chip's specifications are guaranteed for supply voltages ranging from 3.0-5.5 V. Programming and testing are achieved via a 3-terminal bi-directional serial interface and internal registers. Nominal power dissipation at 3.0 V supply and 40 Mb/s data rate is 360 mW. Pulse pairing and write data jitter, two key performance parameters, each measured less than 300 ps.<
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