ESD protection in a mixed-voltage interface and multirail disconnected power grid environment in 0.50- and 0.25-/spl mu/m channel length CMOS technologies

On-chip ESD protection for semiconductor chips with mixed-voltage interface applications and internal multiple power bus architecture is discussed. ESD robustness in shallow trench isolation 0.50- and 0.25-/spl mu/m channel-length CMOS technologies is demonstrated using novel ESD structures.<
>