I/sub DDQ/ design and test advantages propel industry

The I/sub DDQ/ test method measures the quiescent power supply current of CMOS ICs for select test vectors, or logic states, and provides a clear indication of defects, failure mechanisms, and many types of design errors. Underlying this type of test are design principles that inherently provide high defect coverage, as well as diagnosis capability and physical localization. The ability of I/sub DDQ/ testing to rapidly gauge an IC's health is like a nurse taking a patient's temperature. This is an especially appropriate analogy because it underscores that I/sub DDQ/ testing is not a panacea. As with a patient, other "vital signs" are needed. The authors give a unique perspective into the design of a submicron-technology microprocessor (approximately 1 million transistor, 1OO MHz-plus design). Stringent testability and quality goals drove their selection of I/sub DDQ/ testing in addition to at-speed functional testing, boundary scan, internal scan, and built-in self-test. They demonstrate the many benefits of I/sub DDQ/ testing, including substantially reduced power consumption and the ability to merge readily with other testability and high-performance goals.<
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