A high performance 0.35 /spl mu/m logic technology for 3.3 V and 2.5 V operation

A 0.35 /spl mu/m logic technology has been developed with high performance transistors and four layers of planarized interconnect. A 3.3 V BiCMOS version is used for compatibility with 3.3 V and 5.0 V I/Os. A 2.5 V CMOS version is used for increased performance, lower power and lower cost. 3.3 V CMOS devices have channel lengths of <0.25 /spl mu/m and 2.5 V devices have channel lengths of <0.20 /spl mu/m. Using a CV/I performance metric, these are the fastest devices reported to date using 0.35 /spl mu/m lithography. 1 Mbit SRAMs have been built using this technology with a 20.5 /spl mu/m/sup 2/ 6 T cell size.<
>