18 ps ECL-gate delay in laterally scaled 30 GHz bipolar transistors

ECL-gate delays as low as 18 ps have been achieved in conventional bipolar technology, with a cut-off frequency f/sub T/ of 30 GHz. Rather than optimizing vertical doping profiles for maximum f/sub T/, the transistors were optimized for high-speed circuit performance by reducing device parasitics. This simplifies their integration in BICMOS processes and, since lower f/sub T/s are achieved at lower current densities, allows a decreased power consumption for high-speed circuits. In this transistor technology a DC-coupled broad-band amplifier (BBA), with a record bandwidth of 11.7 GHz for 15 Gbit/s optical data links has been fabricated.<
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