Ta/sub 2/O/sub 5/ capacitors for 1 Gbit DRAM and beyond

A thermally robust Ta/sub 2/O/sub 5/ capacitor applicable to the 1 Gbit DRAM and beyond was developed. From the degradation-free Ta/sub 2/O/sub 5/ capacitor with a TiN/poly-Si top electrode, the sputtered-TiN was replaced by the PECVD-WN to improve the step coverage for the complicated capacitor structure. The Ta/sub 2/O/sub 5/ capacitor with a PECVD-WN/poly-Si top electrode had a better thermal stability in the complicated capacitor structure than that with sputtered-TiN/poly-Si, as a result. Capacitance of more than 90 fF/cell and leakage current lower than 2/spl times/10/sup -15/ A/cell were obtained by applying the WN/poly-Si top electrode and a 3.5 nm Ta/sub 2/O/sub 5/ capacitor dielectric to a cylindrical capacitor with rugged poly-Si surface (projection area=0.4 /spl mu/m/sup 2/). TDDB measurement predicted longer lifetime than 10 years at the device operating voltage. This new capacitor structure, therefore, surpasses the requirements for the 1 Gbit DRAM.<
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