Hierarchical mapping of spot defects to catastrophic faults-design and applications

This paper describes the defect to fault mapper (DEFAM), and its use in integrated circuit test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects on a design during the manufacturing process, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the required analysis effort. It also reports faults in terms of the design hierarchy, which is essential for many applications. Yield analysis results are given for CMOS designs of up to 164 K transistors. Test quality analysis results are given for an adder module.<
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