Analog VLSI design of cellular neural networks with annealing agility

Local interconnection and simple synaptic operators are the most attractive features of the CNN for VLSI implementation in high-speed, real-time applications. Several hardware implementations of the CNN have been reported in the literatures. The CMOS VLSI design of a continuous-time shift-invariant CNN with digitally-programmable operators is considered. In addition, the circuits for hardware annealing is included to provide the flexibility of the network in a variety of applications.<
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