A 400 MHz, 300 mW, 8 kb, CMOS SRAM macro with a current sensing scheme

This paper describes the development of a 400 MHz, 8 kb, 0.4 /spl mu/m CMOS SRAM macro targeted for use in on-chip cache memories. A newly developed pipeline scheme uses a dynamic decoder and half-latches to increase speed by 10% over that of conventional synchronous pipeline SRAMs. Further, a newly developed current sensing scheme, resistant both to noise and to process deviations, contributes to a job reduction in power dissipation.<
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