Hardware efficient learning on a 3-D optoelectronic neural system

Discusses the dual-scale topology optoelectronic processor (D-STOP) neural network, a scalable, optically interconnected neural network architecture. The authors present the tandem D-STOP system, which provides the connectivity needed for building fully-parallel neural networks with generic gradient-descent learning rules. The authors review the content addressable network (CAN) learning algorithm, a discrete learning algorithm that provides accelerated learning with reduced hardware requirements. The authors then show how the CAN algorithm can be effectively mapped onto D-STOP, and they investigate associated optoelectronic hardware tradeoffs.<
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