Long-term bias temperature reliability of P/sup +/ polysilicon gated FET devices

An instability was found to be associated with +BT stress for P/sup +/ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N/sup +/ poly-gated devices (NNMOS and NPMOS). The instability with the P/sup +/ poly-gated devices, which is a decrease in threshold voltage (V/sub t/) and an increase in interface state density (D/sub it/), was significantly reduced following N/sub 2/ annealing at 400/spl deg/C. It is shown that adequate reliability for P/sup +/ poly-gated devices can be achieved for VLSI technologies.<
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