Analysis of gate oxide thickness hot carrier effects in surface channel P-MOSFET's

The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the oxide thickness is reduced from 10.7 nm to 7.2 nm for stress at low gate voltages (peak electron injection conditions), with no corresponding change in hot carrier resistance at high gate biases. Using a number of techniques, the various possible factors responsible for this are examined, and it is concluded that the increase in hot carrier resistance arises primarily due to a change in the position of hot electron injection peak, which moves further into the drain junction region for the thinner oxide transistors. Such effects as field-induced detrapping and the direct reduction in /spl Delta/V/sub t/ for thinner oxides are found to play secondary roles.<
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