Mechanical and electrical evaluation of a bumped-substrate die-level burn-in carrier

A high-yield die supply has been identified as a key requirement for the viability of commercial multichip modules (MCM). The result of die or wafer level test and burn-in, (beyond the level of historical wafer probe), to provide dice with performance and reliability levels equivalent to single chip packaged dice is commonly called known good die (KGD). There are many proposed methods to obtain KGD, at varying levels of maturity, and with varying levels of cost, complexity, and potential impact on device performance and reliability. In this paper, we describe the mechanical and electrical evaluation of a temporary die-level burn-in carrier designed for use in providing known good dice. Three device types are used in this evaluation to explore the limitations of the carrier system under evaluation: a 1 M DRAM, a 128 k/spl times/8 SRAM, and a 56 k gate ASIC. Die size, and bond pad count, size and pitch all impact the applicability of the carrier system under evaluation. Mechanical evaluations performed to date include measurements of critical carrier features such as bump height, die alignment structure placement and bond pad damage caused by the carrier contacts. Electrical evaluations include continuity and electrical test performance at multiple temperatures.<
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