Wire bonds over active circuits

A reliable process-for wire bonding over active integrated circuits, which are subsequently assembled in plastic packages, has been developed. This technology accommodates reducing the silicon die area required for bond pads and for on-chip bussing. Further, it supports area array wire bonding by allowing larger bond pads with relaxed pitch without sacrificing silicon area. This is accomplished by processing an additional metal layer on the wafer's protective overcoat for bond pad and bussing metallization. A stress buffer layer of polyimide is applied between the inorganic overcoat and top metal layer. Material characteristics and process requirements that are fully compatible with existing wafer fabrication technology and the wire bond technology required for assembly are defined. Design rules for implementing the process in new chip designs are given. Accelerated reliability tests performed on double-level metal logic devices show no degradation due to these new processes.<
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