ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed.<
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