A 0.6 /spl mu/m/sup 2/ 256 Mb trench DRAM cell with self-aligned BuriEd STrap (BEST)

In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd STrap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605/spl mu/m/sup 2/ at 0.25 /spl mu/m design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells. The BEST cell concept, process, and design, as well as preliminary results obtained from a 256 Mb DRAM development test chip, processed with optical lithography down to 0.25 /spl mu/m design rules, are presented in this paper.<
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