Electrothermal simulation of electrical overstress in advanced nMOS ESD I/O protection devices

For electrical overstress (EOS) and electrostatic discharge (ESD) reliability of submicron ICs, there are currently no available accurate circuit-level simulation tools to analyze and design input/output protection devices. In this paper, we introduce a unique circuit-level electrothermal simulator that can accurately predict the protection device behaviour up to the onset of second breakdown under high-current stress events. The results shown here demonstrate practical application to EOS/ESD robustness in sub-micron technologies.<
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