The design of a sigma-delta codec for mobile telephone applications

The algorithmic, structural, and architectural design of a 13-bit linear sigma-delta ADC and DAC for use with digital mobile telephone systems is described. Analog and digital third-order single-loop modulators running at 512 kHz (64X oversampled) are used to keep the power dissipation low. The ADC uses a two-stage decimation process. The first stage uses a fourth-order "slink" filter to reduce the sample rate to 16 kHz. This is implemented very efficiently using a "running sum" decimator. The second stage is implemented using an IIR minimum-phase lowpass filter which also compensates for the frequency gain distortion of the first stage. The interpolation function of the DAC is realised using a minimum-phase IIR lowpass filter operating at 32 kHz which also compensates for the passband distortion of the zero-order-hold rate converters preceding and following the filter. The digital signal processing of the codec is implemented using two processors. One realises the digital modulator and the high data rate part of the slink decimator while the other, a two-instruction RISC processor, handles the remaining operations. The codec has to operate with three different master clock frequencies, 12.8, 13 and 19.44 MHz. A third processor synthesises the 512 kHz convertor clock. The circuit has been fabricated in a nominal 1.2 mu m double-metal double-poly CMOS process. The conformance of the design to the specification was obtained through the use of bit-true functional simulation which acted as bridge between the algorithmic simulation and the logic level simulation.<
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