Low power 13 bit ADCs for ASIC applications

A family of analogue to digital converters are described for system integration ASIC applications. The converter architecture gives a current consumption of 10 mW coupled with an analogue core size of 2 mm/sup 2/. The individual converters maintain 13 bit dynamic range and linearity with a sampling rate of 40 kHz. Area and power consumption of the circuit are optimised for ASIC applications, where mixed analogue and digital circuits are to be implemented on the same die. The converters use a successive approximation algorithm in combination with charge balancing techniques. Self calibration is used to give full linearity for the sampling capacitor arrays. The choice of the architectural partition of the converter gives rise to a compact, rectangular and hence easily route-able analogue core, where the critical circuit components are shielded from the external logic. The standardised logic controller that accompanies the core can be routed in the ASIC flow with the customers' additional logic. For the 10V, 2u CMOS variant, the analogue area is <2 mm/sup 2/, the standard cell logic is <3 mm/sup 2/. For the 5 V, 1.2 mu m CMOS variant, the analogue core is <1.6 mm/sup 2/, the standard cell logic for 5V in 1.2 mu m and 1.0 mu m is, of course, proportionately smaller.<
>