A 13.4-GHz CMOS frequency divider

This paper describes the design ofa 13.4 GHz 1/2-frequency divider fabricated in a partially-scaled 0.1 /spl mu/m bulk CMOS technology. The circuit design is heavily influenced by the device structures and layout rules. To reduce both fabrication cost and turnaround time, the CMOS process scales only channel length to 0.1 /spl mu/m and gate oxide to 40 /spl Aring/. Design rules for other dimensions correspond to a 1 /spl mu/m technology, yielding a minimum source/drain area of 2.2 /spl times/2.2 /spl mu/m/sup 2/. Thus the contribution of the source/drain junction capacitance is substantial, severely limiting speed. The divider described employs the following techniques to improve the speed: 1) nMOSFETs for sensing and regeneration and pMOSFETs for pull-up, 2) no stacked devices and pass gates, 3) ring-shaped geometry for all transistors.<
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