A 3.4 ns 0.8 /spl mu/m BiCMOS 53/spl times/53 b multiplier tree

A 53/spl times/53 b multiplier tree with 3.4 ns latency, 10 mm/sup 2/ active area, and 5 W power dissipation at 200 MHz and 3.6 V supply is implemented in 0.8 /spl mu/m n-well BiCMOS with 115 /spl Aring/ gate oxide, 0.45 /spl mu/m effective channel length, and 4 levels of metal. This 3.4ns low-latency multiplier is for a floating-point unit (FPU) on a BiCMOS RISC processor capable of performing IEEE double precision multiply-add operations in three pipelined stages at 200MHz (15ns latency, 5ns throughput, 400MFLOPs peak rate) using multiply-add fused dataflow.<
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