Design considerations for thin-film SOI/CMOS device structures

Allowable design regions for thin-film SOI/CMOs device structures, taking account for the relation between SOI film thickness and the concentration of SOI substrate impurities, are investigated. Not only are the advantages of thin-film SOI MOSFETs verified, but constraints on threshold voltage and kink-free controls are also shown. Conventional n/sup +/ poly-Si gate NMOSFETs tend to have difficulty in maintaining high transconductance for deep submicrometer gate length because of the constraints of normally-off threshold voltage and kink-free characteristics. By choosing a gate with the same work function as the intrinsic silicon semiconductor, the allowable design regions for deep submicrometer gate SOI MOSFETs are expected to have a low-impurity SOI substrate and an optimized threshold voltage for high-performance SOI/CMOS LSIs. The device scaling for various gate electrodes are also discussed for 1- to 0.2 mu m gate SOI/CMOS devices.<
>