An 11000-fuse electrically erasable programmable logic device (EEPLD) with an extended macrocell

A high-performance electrically erasable programmable logic device (EEPLD) has been designed and fabricated using a 1.5- mu m n-well CMOS technology. The chip has 11040 fuses which are used not only in the logic array but also in the input/output macrocell. Typical access time for the nonregistered version is 35 ns with a power dissipation of 450 mW. There are 16 input/output macrocells which are architecturally defined by 128 electrically programmable fuses. Die size is 130*230 mils.<
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