SWEC speeds VLSI simulation

A new simulator called SWEC (StepWise Equivalent Conductance) can efficiently simulate circuits with MOS transistors and passive elements. SWEC adopts four novel techniques: 1) stepwise equivalent conductance implicit integration, 2) piecewise-linear waveform event-driven simulation, 3) recursive convolution formulation based on the Pade approximation, and 4) interconnect partition, to achieve significant speed-ups over existing simulators. The first two timing simulation techniques are briefly reviewed in this article.<
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