Enhanced high-frequency performance in a GaAs, self-aligned, n-JFET using a carbon buried p-implant

C ion implantation has been employed, for the first time, to form the buried p-layer in GaAs, self-aligned, ion implanted JFETs. Comparable DC performance was seen for JFETs with C or Mg implants; however, C-backside JFETs showed superior high-frequency performance. High dose C-backside devices had a f
_T
of 28.3 GHz and a f
_max
of 43.2 GHz for a 0.5 μm gate length that were 28% and 46% higher, respectively, than comparable Mg-implanted JFETs. This enhancement is a result of the lower C/sub gs/ in the C-backside device resulting from he inherently low activation of the implanted C below the channel while the C still effectively compensated the tail of the Si-channel implant. This approach relaxes the trade-off between optimizing the DC and the AC performance for the buried p-implant in GaAs JFETs and MESFET's.