Submicron BiCMOS well design for optimum circuit performance

The optimization of a submicron BiCMOS well design is described. The use of buried layers, a thin intrinsic epi layer, and a double n-well implant creates steeply graded well profiles which result in improved circuit performance due to lower diode capacitance. High contact resistance to the buried n+ layer is avoided by using a novel polysilicon plug contact process which also eliminates lateral n+ diffusion, enabling the base-to-collector design rule to be shrunk by more than 25%.<
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