0.3-/spl mu/m mixed analog/digital CMOS technology for low-voltage operation

A 0.3-/spl mu/m mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si/sub 3/N/sub 4/ capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm.<
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