Trench isolation technology with 1 /spl mu/m depth n- and p-wells for a full-CMOS SRAM cell with a 0.4 /spl mu/m n/sup +p/sup +/ spacing

This paper shows that 0.7 /spl mu/m depth shallow trench isolation with SiO/sub 2/ filling can achieve 0.4 /spl mu/m n+/p+ spacing, utilizing shallow p- and n-wells formation with retrograde profiles. An 80 degree taper trench with rounded edge accompanied by HCl ambient oxidation improves subthreshold characteristics and junction leakage. A 7.65 /spl mu/m/sup 2/ full-CMOS cell competitive to TFT cell size at 0.35 /spl mu/m design rule has been realized and a 256k bit SRAM has been fabricated.<
>