Cornerless active area cell and Bi-T-MOS process for sub-half micron SRAMs

This paper presents a novel memory cell and process technology. The memory cell adopts the symmetry layout which has cornerless active area, a single bent word line and common gate TFTs. Furthermore, this memory cell realizes large cell ratio using a direct contact off-set resistance. The proposed process technology is optimization of bipolar, TFT and CMOS process (Bi-T-MOS). The Bi-T-MOS technology decreases the poly-silicon layers to triple-level without decreasing performance of the transistors.<>