A new capacitor on metal (COM) cell for beyond 256 Mbit DRAM

We propose an advanced DRAM cell structure with a capacitor formed after patterning the first-level metal. Since the second-level-metal which will be patterned after forming storage capacitors usually has a relaxed design rule, a sufficient cell capacitance can be obtained in this structure by simply increasing the stack height of the capacitor. A limited thermal cycle after the storage node formation makes it possible to use Ta/sub 2/O/sub 5/ as a dielectric material without causing high temperature related leakage problems.<
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