Data retention in ultra-thin-film-SOI DRAM with buried capacitor cell

Data retention in DRAM cells with ultra-thin bonded SOI film is investigated using 256 kbit fully functional test chip of 0.4 /spl mu/m design rule. In order to minimize an accumulation of minority carriers in channel region, we adopt a PMOS cell transistor. As a result, a retention time of 47 seconds for 50% bit fail at 25/spl deg/C, which is determined by a subthreshold diffusion current in the cell transistor, is obtained. A possibility of further improvement in retention time is then discussed. An importance of an elimination of GIDL is also pointed out.<
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