Integration of ferroelectric capacitor technology with CMOS

Ferroelectric technology has several desirable features for low-power nonvolatile memories including low operating voltages (read and write as low as 1.5 V), high-speed write operation (intrinsic switching times <2 ns), long-term endurance (>10/sup 13/ read/write cycles), and small cell size (potentially near DRAM densities). Realization of practical memories employing ferroelectric technology requires successful integration with CMOS. However, very little has been reported on the process integration issues unique to ferroelectric technology. This paper is the first detailed report of these integration issues. The paper discusses the impact of CMOS backend processing on ferroelectric capacitors as well as the effect of capacitor fabrication on transistor characteristics.<
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