An ultra-thin fully depleted floating gate technology for 64 Mb flash and beyond

In high density flash memories such as 8 Mb and 16 Mb, a stacked single transistor cell, which is programmed with channel hot-electron injection and erased with Fowler-Nordheim tunneling from the source side, is a key technology. However, cell size reduction and decrease of power consumption are required in order to realize higher density and 3 V-single power supply flash memories. In this paper, we propose a flash memory cell with an ultrathin and non-dope floating gate which is fully depleted and acts as dielectric film. Due to its dielectric nature, programming speed can be improved by factor two compared with a connectional cell. These characteristics can reduce power consumption of programming. Because the ultra-thin floating gate with thickness of about 100 /spl Aring/ minimizes field oxide loss, a cell size of 1.3 m/sup 2/ can be easily achieved, which is 25% smaller than a conventional one with a same design rule. Furthermore, a possibility of replacing ONO interpoly dielectric film by a single layer oxide film with thickness of 100/spl Aring/ is demonstrated.<
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