Optimizing compiled Verilog

While optimization of traditional programming languages is reasonably well understood, optimization of hardware description languages is much less so. Hardware description languages provide both a different set of problems and a different set of opportunities for optimization. On the problem side, hardware models tend to be very large compared to software applications. As a result, the optimizer (which is typically a memory hog even on modest applications) must focus carefully on memory usage. On the opportunity side, hardware models tend to have much simpler control flow than do software applications. This permits a more efficient set of analysis techniques/spl minus/techniques that are not possible in compilers for high level languages. The paper discusses the ways in which traditional compiler optimization techniques have been adapted in a compiler for Verilog.<>