A hierarchical interconnection structure for field-programmable gate arrays

A new interconnection structure for FPGAs is presented. The structure is hierarchically divided into two levels. Four adjacent logic blocks are grouped together at the first level, and then the group is connected to a bus structure at the second level. The functionality of a logic block is enhanced so that less logic blocks are needed and interconnections are simplified. Therefore, the performance of the FPGA is much improved.<>